This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-215290, filed Jul. 17, 2000; and No. 2001-051439, filed Feb. 27, 2001, the entire contents of both of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a power semiconductor device, such as a vertical power MOSFET, and a method of manufacturing the same.
2. Description of the Related Art
The on-resistance of a vertical power MOSFET depends largely on the electric resistance of the conduction layer (drift layer) part. The dopant concentration that determines the electric resistance of the drift layer is restricted by the breakdown voltage of the p-n junction formed by the body and the drift layer and cannot be raised above the limit. Therefore, there is a tradeoff relationship between the element breakdown voltage and the on-resistance. It is important to improve the tradeoff in decreasing the power loss of a power semiconductor device. The tradeoff has a limit determined by the element material. Exceeding the limit is a key to realizing a low on-resistance element that outperforms the existing power elements.
One known method of realizing a low on-resistance that exceeds the limit of the material is to use an element structure where an insulating layer having a shape for trapping carriers, such as a buried layer made of an oxide layer, is buried in a drift layer (for example, Holger Kapers et al., xe2x80x9cDielectric Charge Traps: A New Structure Element for Power Devicesxe2x80x9d, ISPSD""2000, May 22-25, Toulouse, France, pp. 205-208).
The literature has disclosed a configuration where a plurality of charge traps are provided in a power element and described the effect using simulation. To put the configuration to practical use, however, it is necessary to determine the structure of concrete charge traps and establish a method of manufacturing the charge traps.
This invention was made considering the above situation. Therefore, the object of the present invention is to provide a power semiconductor device capable of improving the tradeoff between the element breakdown voltage and the on-resistance and a method of manufacturing the same.
The foregoing object is accomplished by providing a power semiconductor device comprising: a first semiconductor layer of a first conductivity type having a first and a second main surface that oppose to each other; a first main electrode electrically connected to the second main surface of the first semiconductor layer; a second semiconductor layer of a second conductivity type selectively formed on the first main surface of the first semiconductor layer; a third semiconductor layer of the first conductivity type selectively formed on the surface of the second semiconductor layer; a second main electrode electrically connected to the surface of the second semiconductor layer and a surface of the third semiconductor layer; a gate electrode formed via a gate insulating film above the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer; and buried layers whose cross section is shaped like a letter U and which are made of either an insulating layer or a semiconductor layer having a wider bandgap than that of the first semiconductor layer and are provided in the first semiconductor layer in such a manner that a set of at least two of the buried layers are arranged with a pitch of d and a spacing of g in a horizontal direction perpendicular to a vertical direction passing through the first main electrode and the second main electrode and at least one stage of the set of at least two buried layers is arranged in the vertical direction, wherein a ratio A of a product of a height H of the U-shaped buried layers and the arrangement pitch d to the spacing g between adjacent ones of the U-shaped buried layers is expressed as:
A(=Hd/g)xe2x89xa613.2
With this configuration of the power semiconductor device, the ratio B of the sum of the width W and height H of the U-shaped buried layers to the arrangement pitch d is expressed as:
B(=(W+H)/d)xe2x89xa60.3
A power semiconductor device manufacturing method according to the present invention comprises: a first step of forming a fourth semiconductor layer having a third and a fourth main surface that oppose to each other; a second step of forming a trench whose cross section is shaped like a letter U by etching the third main surface of the fourth semiconductor layer; a third step of forming U-shaped buried layers by implanting oxygen or nitrogen ions into an inner wall face of the trench; a fourth step of forming a fifth semiconductor layer of a first conductivity type whose surface is flat on the fourth semiconductor layer including the inside of the trench; forming an (n+4)-th semiconductor layer of the first conductivity type at the top surface by repeating the first to the fourth step n times (n is an integer) and thereby forming a first stacked semiconductor layer where the fourth semiconductor layer is at a bottom and the (n+4)-th layer is at the top; forming a first main electrode electrically connected to a second main surface of the first stacked semiconductor layer, which is equal to the fourth main surface of the fourth semiconductor layer, after the forming of the first stacked semiconductor layer; selectively forming a second semiconductor layer of the second conductivity type on a first main surface of the first stacked semiconductor layer after the forming of the first stacked semiconductor layer; selectively forming a third semiconductor layer of the first conductivity type on a surface of the second semiconductor layer; forming a second main electrode so as to be joined to the surface of the second semiconductor layer and a surface of the third semiconductor layer; and forming a gate electrode via a gate insulating film above the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer.
Furthermore, a power semiconductor device according to the present invention comprises: a first semiconductor layer of a first conductivity type having a first and a second main surface that oppose to each other; a first main electrode electrically connected to the second main surface of the first semiconductor layer; a second semiconductor layer of a second conductivity type selectively formed on the first main surface of the first semiconductor layer; a third semiconductor layer of the first conductivity type selectively formed on a surface of the second semiconductor layer; a second main electrode formed so as to be joined to the surface of the second semiconductor layer and a surface of the third semiconductor layer; a gate electrode formed via a gate insulating film above the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer; and a plurality of buried layers buried in the first semiconductor layer, each of the buried layers having a stacked film of an insulating layer shaped substantially like a letter U and a polysilicon layer formed on the insulating layer.
Furthermore, a power semiconductor device according to the present invention comprises: a first semiconductor layer of a first conductivity type having a first and a second main surface that oppose to each other; a first main electrode electrically connected to the second main surface of the first semiconductor layer; a second semiconductor layer of a second conductivity type selectively formed on the first main surface of the first semiconductor layer; a third semiconductor layer of the first conductivity type selectively formed on a surface of the second semiconductor layer; a second main electrode formed so as to be joined to the surface of the second semiconductor layer and a surface of the third semiconductor layer; a gate electrode formed via a gate insulating film above the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer; and a plurality of buried layers which are buried in the first semiconductor layer and each of which is made of either an insulating layer or a semiconductor layer having a wider bandgap than that of the first semiconductor layer and has a side and a bottom part with a U-shaped cross section and a cap part with an opening smaller in inside diameter than the side part of the U-shaped part.
Furthermore, a power semiconductor device according to the present invention comprises: a first semiconductor layer of a first conductivity type which has a first and a second main surface that oppose to each other and further has a central region in which an active element is formed and a termination region enclosing the central region; a first main electrode electrically connected to the second main surface of the first semiconductor layer; a second semiconductor layer of a second conductivity type selectively formed in the central region of the first main surface of the first semiconductor layer; a third semiconductor layer of the first conductivity type selectively formed at the surface of the second semiconductor layer; a second main electrode electrically connected to the surface of the second semiconductor layer and a surface of the third semiconductor layer; a gate electrode formed via a gate insulating film above the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer; a plurality of first buried layers whose cross section is shaped like a letter U and which are made of either an insulating layer or a semiconductor layer having a wider bandgap than that of the first semiconductor layer and are provided in the first semiconductor layer in such a manner that at least two of the first buried layers are arranged in a horizontal direction perpendicular to a vertical direction passing through the first main electrode and the second main electrode and at least one stage of a set of at least two first buried layers is arranged in the vertical direction; and a plurality of second U-shaped buried layers provided in the first semiconductor layer in the termination region, wherein shapes and arrangements of the plurality of second U-shaped buried layers are different from those of the plurality of first U-shaped buried layers in the central region.
Furthermore, a power semiconductor device according to the present invention comprises: a first semiconductor layer of a first conductivity type having a first and a second main surface that oppose to each. other; a first main electrode electrically connected to the second main surface of the first semiconductor layer; a second semiconductor layer of a second conductivity type selectively formed on the first main surface of the first semiconductor layer; a third semiconductor layer of the first conductivity type selectively formed on a surface of the second semiconductor layer; a second main electrode electrically connected to the surface of the second semiconductor layer and a surface of the third semiconductor layer; a gate electrode formed via a gate insulating film above the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer; anyone selected from the group consisting of buried layers whose cross section is shaped like a letter U and which are made of either an insulating layer or a semiconductor layer having a wider bandgap than that of the first semiconductor layer, and a fourth semiconductor layer of the second conductivity type; and a Schottky barrier diode provided on the first semiconductor layer and connected in parallel with a built-in diode formed between the second semiconductor layer and the first semiconductor layer.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.